[Software Optimization and Reconstruction] Compiler driven data layout optimization for regular/irregular array access patterns, ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), and also appears in ACM SIGPLAN Notices, Jun 2008

 

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International Papers

Application Specific Architectures Memory Access Optimization in Compilation for Coarse Grained Reconfigurable Architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), Oct 2011 (Acceptance rate: 25%)
Application Specific Architectures I2CRF : Incremental Interconnect Customization for Embedded Reconfigurable Fabrics, Design Automation and Test in Europe (DATE), Mar 2011
Application Specific Architectures VLIW processor for H.264 : Integer transform and Quantization, International SoC Design Conference (ISOCC), Nov 2010
Application Specific Architectures An Asip Approach for Motion Estimation Reusing Resources for H.264 Intra Prediction, International SoC Design Conference (ISOCC), Nov 2010
Application Specific Architectures Implementing Dynamic Implied Addressing Mode for Multi-Output Instructions, International Conference on Compiler, Architecture and Synthesis for Embedded Systems (CASES), Oct 2010
Application Specific Architectures Two Versions of Architectures for Dynamic Implied Addressing Mode, Journal of Systems Architecture (JSA), May 2010
Application Specific Architectures Operation and Data Mapping for CGRA, ACM SIGPLAN/SIGBED Conference on Languages, Compiler and Tools for Embedded Systems (LCTES), Apr 2010
Application Specific Architectures Operation and data mapping for CGRAs with multi-bank memory, ACM Sigplan Notices 45 (4), 17-26, Apr 2010
Application Specific Architectures Memory-Aware Application Mapping on Coarse Grain Reconfigurable Arrays, International conference on High-Performance Embedded Architectures and Compilers (HiPEAC), Feb 2010
Application Specific Architectures Application-Specific Instruction Set Processor For H.264 On-Chip Encoder, International SoC Design Conference (ISOCC), Nov 2009
Application Specific Architectures A new addressing mode for the encoding space problem on embedded processors, 7th IEEE Symposium on Application Specific Processors (SASP), Jul 2009
Application Specific Architectures Orthogonal Instruction Encoding for a 16-bit Embedded Processor with Dynamic Implied Addressing Mode, International Symposium on Advances of High Performance Computing and Network (AHPCN), Jun 2009
Application Specific Architectures Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Mar 2009
Application Specific Architectures A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Mar 2009
Application Specific Architectures Register File Power Reduction Using Bypass Sensitive Compiler, IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), Jun 2008
Application Specific Architectures Hiding Cache Miss Penalty Using Priority-based Execution for Embedded processors, Design Automation and Test in Europe (DATE), Mar 2008
Application Specific Architectures SPKM: A Novel Graph Drawing based Algorithm for Application Mapping onto Coarse-Grained Reconfigurable Architectures, Asia and South Pacific Design Automation Conference(ASP-DAC), Jan 2008
Application Specific Architectures HW/SW co-design for embedded system using UML, International Conference on Ubiquitous Information Technologies & Applications (ICUT), Dec 2007
Application Specific Architectures Automatic Design Space Exploration of Register Bypasses in Embedded Processors, IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), Nov 2007
Application Specific Architectures Efficient Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm, Workshop on Application Specific Processors (WASP), Sep 2007 (Best paper, invited for IEEE Transactions on VLSI)