[Application Specific Architectures] Power-conscious Configuration Cache Structure and Code Mapping for Coarse-grained Reconfigurable Architecture, International Symposium on Low Power Electronics Design (ISLPED), Oct 2006

 

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International Papers

Software Optimization and Reconstruction Automatic Parallelization for Non-cache Coherent Multiprocessors, Languages and Compilers for Parallel Computing, also appear in Lecture Notes in Computer Science, Vol. 1239, pp. 266-284, Springer-Verlag, Aug 1996
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