[Application Specific Architectures] Bypass Aware Instruction Scheduling for Register File Power Reduction, ACM SIGPLAN conference on Languages, Compilers, Tests of Embedded Systems, Jun 2006 (Best paper, invited for ACM Transactions on Embedded Computing Systems)

 

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International Papers

Software Optimization and Reconstruction Automatic Parallelization for Non-cache Coherent Multiprocessors, Languages and Compilers for Parallel Computing, also appear in Lecture Notes in Computer Science, Vol. 1239, pp. 266-284, Springer-Verlag, Aug 1996
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